The present invention relates generally to programmable logic devices (PLDs), and in particular to various circuit techniques to provide dedicated exclusive OR (XOR) function in complex PLDS.
Programmable logic devices are digital, user-configurable integrated circuits used to implement custom logic functions. For the purposes of this description, the term PLD encompasses all digital logic circuits configured by the end-user, including programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), erasable and complex PLDs and the like. Such devices are sometimes referred to as, for example, PALs, FPLAs, EPLDs, EEPLDs, LCAs, CPLDs, and FPGAs. The basic building block of a PLD is the logic cell, sometimes referred to as a macrocell. Typically, a logic cell contains combinatorial logic as well as a programmable flipflop to implement sequential logic. One class of PLDs commonly employs a sum-of-products structure to implement logic functions. In such PLDS, the combinatorial logic in each logic cell includes a set of wide-input AND gates that generate the product terms or p-terms. The p-terms are then fed into the inputs of an OR gate to compute the sum. Since all combinatorial logic can be reduced to a sum-of-products expression, the AND-OR array can produce any Boolean function. Highly complex logic functions can be implemented by combining or cascading large numbers of such logic cells.
One logic function that a p-term based structure cannot implement very efficiently is a wide exclusive OR type circuit. It is to be understood that the terminology "exclusive OR type circuit" refers to both exclusive OR (XOR) and exclusive NOR (XNOR) gates. A typical logic function that requires a wide XOR or XNOR is a parity checker or parity generator. A parity bit is set or reset by the output of a wide XOR gate that receives multiple data bits at its inputs. In conventional p-term based PLDS, implementing such a parity generator requires a large number of p-terms and therefore quite a few logic cells. Using as an example the basic logic cell in Altera's MAX 7000 PLD, implementing an 8 bit XOR would require a total of 65 p-terms. A 65 p-term solution uses the already existing XOR gate in each logic cell and the parallel expander feature of the device. With 5 p-terms per logic cell, this XOR uses 13 logic cells to implement. A less logic intensive approach would use two logic cells each implementing a 4-bit XOR, with their outputs fed into a third logic cell to perform another level of XOR on the signals. This solution uses three logic cells, but is considerably slower since it requires two stages of logic. Thus, implementing wide XOR with conventional p-term based PLD logic cells is either costly in terms of amount of logic required or slow. In one embodiment the present invention provides an improved programmable logic device with a LAB-based wide AND gate for enhanced LAB functionality as well as associated methods of operation. There is therefore a need for p-term based PLDs with faster and more efficient wide XOR capability.
PLDs, while similar in some aspects of overall functionality, may be of very different types in terms of circuit architecture. One family of PLDs uses a sum-of-products (SOP) architecture whereby each output is the ORed sum of a number of ANDed product terms of the inputs. This family is represented by the Altera MAX.RTM. and CLASSIC.TM. 5000 EPLDs. Another family of PLDs uses look-up tables (LUTs) to perform logic functions. This family is represented by the Altera FLEX.RTM. EPLDs.
Modern PLDs generally are constructed from small functional units variously referred to as logic modules or macrocells and herein referred to as logic elements (LEs). These LEs are typically identical or nearly identical throughout the PLD and perform a function that is a sub unit of the function of the entire PLD. For example, in a PLD based on an LUT architecture, the LEs might each be four input/one output LUTs. PLDs generally include an interconnect structure of conductors to provide a mechanism for selectively connecting the inputs and outputs of the LEs in order to perform the PLD functionality.
Larger PLDs of both the SOP and LUT type generally group the smaller LEs into larger functional units herein referred to as logic array blocks (LABs). The LABs can contain within them a local LAB interconnect that allows signals in one LE to be selectively connected to signals in a different LE in the same LAB and that transmits signals from the global interconnect to the inputs of the individual LEs. The LABs may be connected to one another and to input and output circuits by means of the global interconnect.
While such devices have met with substantial success, such devices also meet with certain limitations.
For example, PLDs with a LAB-based structure typically group a number of LEs together into one LAB, in a specific embodiment each LAB has eight LEs. Each LE generally has one output which is a programmable function of its inputs. A typical number of inputs for an LE is four. A typical prior art LAB thus has eight outputs, one output for each of its eight LEs. In such a prior art LAB, the eight outputs are generally not combinable in that LAB. If a user wishes to have a function that is a logical combination of the outputs of a LAB, the outputs of that LAB must be routed through the global interconnect to another LAB in the PLD and made the inputs to another LE which may then combine the signals. This results in an additional level of delay for these logic signals and in use of additional LEs on the PLDs which then can't be used for other functions.
From the above it is seen that an improved programmable logic device is desired.